The following invention relates to a driving architecture for a thin-film electroluminescent (TFEL) display panel comprising a matrix of luminescent pixels.
TFEL display panels are relatively thin panels for use with computer-based systems for displaying both graphic and alphanumeric data. The typical TFEL display panel includes two sets of orthogonally-disposed elongate electrodes usually referred to as scanning and data electrodes, respectively, separated by dielectric layers, and a layer of luminescent material such as ZnS sandwiched between the dielectric layers. The intersections between the two sets of orthogonally-disposed scanning and data electrodes comprise a matrix of pixels which form electroluminescent spots on the display panel. The pixels emit light when the voltage across both electrodes defining each pixel in the matrix assumes an appropriate voltage level sufficient to create an electric field which will cause the ZnS layer to emit light.
The arrays of scanning and data electrodes, respectively, are driven by individual integrated circuit driving amplifiers. These IC's present a largely resistive load to the driving voltage sources. Since the scanning and data electrodes are separated by dielectric layers, the pixels (the intersections between scanning and data electrodes) are capacitive. Electrically, the display panel can thus be modeled as an RC network. Each pixel point reached by each electrode represents a resistance in parallel with a capacitance between it and the adjacent crossing electrode, which may be modeled as a single series RC network for the entire panel.
This electric configuration poses two primary problems for the designer. First, being an RC network, the capacitor element requires a finite time to charge to a voltage level sufficient to cause luminescence of the pixel. Second, the power consumed by the panel varies with the square of the charging voltage. This results from the following analysis:
If an ideal stepped voltage source drives this RC network, the energy stored in the capacitive element after a time T is: EQU W.sub.C =1/2 CV.sup.2.
As the capacitive element charges, current flows through the resistive element and the energy dissipated in the resistor is: ##EQU1## where ##EQU2## Evaluation of the integral gives the result: EQU W.sub.R =1/2 CV.sub.2.
Combining the energy stored in the capacitor, and the energy dissipated through the resistor gives the total amount of energy drawn from a voltage source charging the panel as: EQU W.sub.TOT =CV.sup.2.
If the capacitor is then discharged to ground through the series resistance, the stored energy of 1/2 CV.sup.2 is dissipated in the resistance and thus the entire amount of energy supplied by the voltage source is converted to heat.
Data is generally written on a TFEL panel by precharging the row electrodes a line at a time, to a voltage level just below the threshold level of luminescence. As each line electrode is charged or scanned, a set of data pulses are placed on each of the column electrodes in selective fashion to energize preselected pixels in that line. The data voltage, frequently referred to as a modulation voltage, raises the voltage level of the pixels along the precharged row electrode past the point of Iuminescence. The modulation voI tage component is responsible for the largest share of the panel's power consumption because it is necessary to apply the modulation voltage to an entire column for each line written; and if there are 256 rows, each column may be charged a maximum of 256 times to complete one frame of data.
A frame of data is defined as the data written on the screen during one sequential scan of all the rows. Since power is equal to work per unit time, the power required to charge the row electrodes during a single frame is a function of the row electode capacitance times the scanning frequency or P=fCV.sup.2. If there are to be 60 frames per second, the scanning frequency is 60. In this equation, the composite row electrode capacitance C is the sum of the capacitance of all of tbe individual pixels in a row. This would equal the pixel capacitance times the number of columns.
The power required to charge the column electrodes as each row is written differs significantly from the amount of power required to charge a row. This is because each time a line or row is written, a significant number of columns must be fully charged. A typical TFEL screen array may contain 256 rows and 512 columns. If one assumes that, for each line of data written, approximately half of the columns receive a data pulse (thereby illuminating half of the pixels in that row), then 256 columns must be fully charged for each row that is written. Typically, the voltage used to precharge the rows (commonly referred to as the write voltage) is on the order of 160 volts. Also typical for this type of addressing scheme is a 50 volt requirement for the modulation voltage. Even though the write voltage is more than three times the modulation voltage, the modulation voltage component consumes the most power because of the aforementioned requirement that a significant number of columns must be charged for each row to be written. Thus it turns out that the power consumed by the charging of the column electrodes during each frame is significantly higher than the power consumed in the precharging step. With a larger screen, this problem is exacerbated because more electrodes would be necessary to maintain the same degree of optical resolution. More data electrodes increase the amount of power consumption.
Energy savings could be utilized during the modulation step if enough time were available to effect a slower charging rate. A slower charging rate will result in less energy being dissipated in the resistive component of the RC line. For example, such an energy-saving technique is disclosed in Ohba, U.S. Pat. No. 4,338,598. In the Ohba patent a precharge voltage is applied to opposite sets of electrodes in two steps, half of the precharge voltage being applied to the scanning electrodes, and half of the precharge voltage being applied to the data electrodes. This technique, however, may extract a penalty in the form of the time required to execute it which may in turn require that the scanning rate or number of frames of data per second, be reduced. This occurs because a finite time is required to charge a column, and the entire length of the column must be charged for each selected column as each row is scanned.
lt would therefore be desirable to implement power reduction techniques for reducing the amount of power consumed in driving the panel without affecting or reducing the scanning rate so that larger TFEL displays could be constructed.